The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting semiconductor device structures including dual epitaxy integration of source or drains for vertical transport field effect transistors having complementary metal oxide semiconductor architectures.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. Some non-planar transistor device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins and side-gates, resulting in increased device density and performance over lateral devices. VFETs are one of the promising alternatives to standard lateral FET structures due to benefits, among others, in terms of reduced circuit footprint. In this type of structure, the current flow is perpendicular to a supporting wafer, unlike the lateral current flow in fin-type FETs (FinFETs).
Complementary metal oxide semiconductors (CMOS) generally use a combination of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. For VFET CMOS, the n-type FET (NFET) uses an n-type doped source or drain (S/D) epitaxy such as phosphorous doped silicon (Si), and the p-type FET (PFET) uses a p-type doped source or drain epitaxy such as boron doped silicon-germanium (SiGe).